SA260324R-0069_r1

SA260324R-0069

① SA Source

• Source: 開啟完整 SA 文章
• Section: SRAM and Memory Hierarchy
• Line hint: 77

Context Before

This brings us to the Groq 3 LPU or LP30, with LPU gen 2 being skipped over. This chip has no Nvidia design involvement. The SerDes issues affecting v2 appear to be fixed. Behind the paywall, we will reveal the SerDes IP vendor which may come as a surprise.

Evidence

Nvidia also announced an LP35 which is a minor refresh of the LP30 which will remain on SF4

Context After

and will require a new tapeout.

② Atomic Claim

Nvidia 也宣布 LP35；它是 LP30 的小幅更新版，並將繼續採用 SF4。

• Epistemic Mode: ASSERTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "frame_type": "CLAIM_ONLY",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "35",
      "30",
      "4"
    ],
    "temporal_mentions": []
  },
  "reason": "LP35 在 canonical registry 中沒有本 claim 可安全使用的明示 canonical target；保留 Nvidia、LP30、SF4 文字但不虛構 LP35 node。",
  "statement": "Nvidia 宣布 LP35，作為 LP30 的小幅更新版，並將維持 SF4 製程。"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
—	—	—

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。