SA260324R-0055_r1

SA260324R-0055

① SA Source

• Source: 開啟完整 SA 文章
• Section: LPU chip
• Line hint: 63

Context Before

However, the Groq LPU 2 was never productized because of design issues.

Evidence

The C2C SerDes on the chip couldn’t hit the advertised 112G speed which caused the design to malfunction, as we detailed long ago in the Accelerator model.

Context After

↗ The third generation Groq LPU is the one that Nvidia will be productizing.

② Atomic Claim

晶片上的 C2C SerDes 無法達到宣稱的 112G 速度，導致設計無法正常運作。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "C2C_SPEED_FAILURE",
  "context_nodes": [
    {
      "id": "04_knowledge_base/Chip-to-Chip Interconnect",
      "label": "C2C"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/SerDes",
    "label": "SerDes"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "112G"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "112G"
    ],
    "value_text": "C2C SerDes 無法達到宣稱的 112G，導致設計 malfunction"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	SerDes	SerDes
context_node	C2C	04_knowledge_base/Chip-to-Chip Interconnect

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。