SA260324R-0039_r1

SA260324R-0039

① SA Source

• Source: 開啟完整 SA 文章
• Section: LPU chip
• Line hint: 51

Context Before

LPU gen 1 was designed on a legacy Global Foundries 14nm process, with Marvell responsible for the chip’s physical design.

Evidence

This was a much more mature node compared to peers when it taped out in 2020, with the incumbent AI chip platforms mostly on TSMC’s N7 platform.

Context After

This made sense for an early product focused on proving out Groq’s architecture and bringing its inference-centric design to market.

② Atomic Claim

這個節點在 2020 年 tapeout 時，相較同業已成熟許多；當時主流 AI 晶片平台大多採用 TSMC 的 N7 平台。

• Epistemic Mode: ASSERTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "comparison_expression": "14nm 在 2020 年 tapeout 時，相較當時多數採用 TSMC N7 的 AI 晶片平台所使用節點更成熟。",
  "entities": [
    {
      "id": "04_knowledge_base/14nm",
      "label": "14nm"
    },
    {
      "id": "04_knowledge_base/7nm",
      "label": "N7"
    }
  ],
  "frame_type": "COMPARISON",
  "metric": "PROCESS_NODE_MATURITY",
  "operator": "MORE_MATURE_THAN",
  "qualifiers": {
    "condition_text": "當時 incumbent AI chip platforms mostly on TSMC N7",
    "numeric_mentions": [
      "2020"
    ],
    "temporal_mentions": [
      "2020"
    ]
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	14nm	14nm
entity	N7	7nm

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。