SA260324R-0029
① SA Source
- Source: 開啟完整 SA 文章
- Section:
LPU chip - Line hint:
43
Context Before
Groq opted for single-level scratchpad SRAM instead of multi-level memory hierarchy to make the hardware execution deterministic.
Evidence
Concretely, LPU architecture has VXM slices for vector operations, MEM slices for loading/storing data, SXM slices for tensor shape manipulation, and MXM slices for performing matrix multiplication.
Context After
Spatially, the slices are laid out horizontally, allowing the data to stream horizontally. Within a slice, instructions are pumped vertically across units. Conceptually, LPU resembles a systolic array that pumps instructions vertically and data horizontally.
② Atomic Claim
具體而言，LPU 架構包含：負責 vector operations 的 VXM slices、負責資料 load/store 的 MEM slices、負責 tensor shape manipulation 的 SXM slices，以及負責 matrix multiplication 的 MXM slices。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "SLICE_TYPES_AND_FUNCTIONS",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "VXM：vector operations；MEM：load/store；SXM：tensor shape manipulation；MXM：matrix multiplication"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | LPU | 04_knowledge_base/Groq LPU |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。