SA260324R-0027_r1

SA260324R-0027

① SA Source

• Source: 開啟完整 SA 文章
• Section: LPU chip
• Line hint: 39

Context Before

Groq’s first and only publicly announced LPU architecture was detailed in their ISCA 2020 paper.

Evidence

Unlike typical hardware architectures connecting many general-purpose cores, Groq re-organized the architecture into groups of single-purpose units connecting to other groups of different purposes, and they named the groups “slices.” Between functional units are streaming registers, scratchpad SRAM for functional units to pass data to each other.

Context After

Groq opted for single-level scratchpad SRAM instead of multi-level memory hierarchy to make the hardware execution deterministic.

② Atomic Claim

不同於把許多通用核心連接起來的典型硬體架構，Groq 將架構重組為不同用途的單一功能單元群組，並把這些群組稱為「slices」；功能單元之間配置 streaming registers 與 scratchpad SRAM，讓功能單元彼此傳遞資料。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "ARCHITECTURE_ORGANIZATION_AND_INTER_UNIT_DATA_PATH",
  "context_nodes": [
    {
      "id": "02_companies/Groq",
      "label": "Groq"
    },
    {
      "id": "04_knowledge_base/SRAM",
      "label": "SRAM"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/Groq LPU",
    "label": "Groq LPU architecture"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": "相對於連接許多 general-purpose cores 的典型硬體架構",
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [],
    "value_text": "以不同用途的單一功能單元群組 slices 組織，功能單元間使用 streaming registers 與 scratchpad SRAM 傳遞資料"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	Groq LPU architecture	04_knowledge_base/Groq LPU
context_node	Groq	Groq
context_node	SRAM	SRAM

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。