NIEK2-0031
① SA Source
- Source: 開啟完整 SA 文章
- Section:
LPU chip - Line hint:
35
Context Before
LPU chip
Groq’s first and only publicly announced LPU architecture was detailed in their ISCA 2020 paper. Unlike typical hardware architectures connecting many general-purpose cores, Groq re-organized the architecture into groups of single-purpose units connecting to other groups of different purposes, and they named the groups “slices.” Between functional units are streaming registers, scratchpad SRAM for functional units to pass data to each other. Groq opted for single-level scratchpad SRAM instead of multi-level memory hierarchy to make the hardware execution deterministic.
Evidence
Conceptually, LPU resembles a systolic array that pumps instructions vertically and data horizontally
Context After
Source: Groq, SemiAnalysis
② Atomic Claim
概念上，LPU 類似 systolic array：指令垂直 pumps，資料則水平流動。
- Epistemic Mode:
ASSERTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"attribute": "UNSPECIFIED_ATTRIBUTE",
"context_nodes": [
{
"id": "04_knowledge_base/Systolic Array",
"label": "systolic array"
}
],
"entity": {
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "概念上，LPU 類似 systolic array：指令垂直 pumps，資料則水平流動。"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | LPU | 04_knowledge_base/Groq LPU |
| context_0 | systolic array | 04_knowledge_base/Systolic Array |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。