clm_ee6f7eea99244d5388cb12185eeca8d7_r1

NIEK2-0175

① SA Source

• Source: 開啟完整 SA 文章
• Section: Inter-node/Intra-rack
• Line hint: 195

Context Before

Source: SemiAnalysis Networking Model ↗

Evidence

This means that each node has 16 x 15 x 2 lanes for inter-node C2C and 2 x 15 lanes for inter-node FPGA which is a total of 510 lanes or 1020 differential pairs (for Rx and Tx)

Context After

Inter-rack

② Atomic Claim

因此每個 node 有 16×15×2 條 inter-node C2C lanes，以及 2×15 條 inter-node FPGA lanes，合計 510 lanes，也就是 1,020 組 differential pairs（Rx 與 Tx）。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "comparison_expression": "因此每個 node 有 16×15×2 條 inter-node C2C lanes，以及 2×15 條 inter-node FPGA lanes，合計 510 lanes，也就是 1,020 組 differential pairs（Rx 與 Tx）。",
  "entities": [
    {
      "id": "04_knowledge_base/Chip-to-Chip Interconnect",
      "label": "C2C"
    },
    {
      "id": "04_knowledge_base/FPGA",
      "label": "FPGA"
    }
  ],
  "frame_type": "COMPARISON",
  "metric": "COUNT",
  "operator": "MULTIPLE_OF",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "16×",
      "15×",
      "2",
      "2×",
      "15",
      "510",
      "1,020"
    ],
    "temporal_mentions": []
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
comparison_entity_0	C2C	04_knowledge_base/Chip-to-Chip Interconnect
comparison_entity_1	FPGA	FPGA

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。