NIEK2-0077
① SA Source
- Source: 開啟完整 SA 文章
- Section:
SRAM and Memory Hierarchy - Line hint:
69
Context Before
Source: Nvidia
Evidence
Context After
One of the benefits of relying on SF4 is that it isn’t constrained like TSMC’s N3, which is putting a cap on accelerator production and is a key reason why the industry remains compute constrained. ↗ This is in addition to not having HBM which is also constrained ↗. This allows Nvidia to ramp production of the LPU without sacrificing or eating into their valuable TSMC allocation or HBM allocations, representing true incremental revenue and capacity that noone else can access.
Since Nvidia has taken over, the next generation LP40 will be fabricated on TSMC N3P and use CoWoS-R, and Nvidia will contribute more of their own IP such as supporting the NVLink protocol rather than Groq’s C2C. This will be the first LPU to be extremely co-designed alongside the Feynman platform. Groq’s original plans for LPU Gen 4 was also with TSMC and Alchip as the back-end design partner. Alchip’s involvement is now redundant with Nvidia able to perform backend design on their own. One of the technical innovations planned is hybrid bonded DRAM to extend on-chip memory with only a slight decrease in latency and bandwidth vs SRAM, but much higher performance compared to DRAM. SK Hynix was tapped as the supplier of the DRAM to be used for the 3D stacking. All of this and more was detailed long ago in the Accelerator model ↗.
② Atomic Claim
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"comparison_expression": "相比之下，LPU 1 配備 230MB SRAM，並提供 750 TFLOPs 的 INT8 運算能力。",
"entities": [
{
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
{
"id": "04_knowledge_base/SRAM",
"label": "SRAM"
},
{
"id": "04_knowledge_base/TFLOPS",
"label": "TFLOPs"
},
{
"id": "04_knowledge_base/INT8",
"label": "INT8"
}
],
"frame_type": "COMPARISON",
"metric": "COMPUTE_PERFORMANCE",
"operator": "COMPARES_WITH",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"1",
"230MB",
"750 TFLOPs"
],
"temporal_mentions": []
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| comparison_entity_0 | LPU | 04_knowledge_base/Groq LPU |
| comparison_entity_1 | SRAM | SRAM |
| comparison_entity_2 | TFLOPs | TFLOPS |
| comparison_entity_3 | INT8 | INT8 |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。