SA260324R-0251
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Rubin Ultra NVL288 - Line hint:
307
Context Before
Each NVLink Switch Chip connects via flyover cables to the connector (144 DPs used x 200 Gbit/s bi-di channel = 28.8Tbit/s) connectors at the edge of the switch blade, and these connectors plug into the midplane board. Nvidia is looking into using co-packaged Copper to reduce loss further, in case NPC doesn’t work. As far as we know the Nvidia is telling supply chain to go for fully co-packaged copper.
Rubin Ultra NVL288
Evidence
Though not officially discussed by Nvidia at GTC 2026, an NVL288 concept has been explored within the supply chain. This would entail two NVL144 Kyber racks placed adjacent to each other, with a rack-to-rack copper backplane used to connect the two racks. One possibility is that all 288 GPUs are connected all to all, but this would require higher radix switches than the current NVLink 7 switches which only offer a maximum radix of 144 ports of 200G.
Context After
If Rubin Ultra NVL288 is deployed, each Rubin Ultra GPU will have a scale-up bandwidth of 14.4Tbit/s uni-di, requiring 144 DPs of cables to connect the NVLink 7 switches. 72 DPs per GPU times 288 GPUs means a total of 20,736 additional DPs required to connect this larger world size domain. This entails a lot of cables, so it is an upper bound of how much cable content could be used.
The radix of the 28.8T NVLink Switch limits the number of GPUs that each switch can connect while still providing for cross-rack connectivity. Either a higher radix switch will have to be used - or there will have to be a degree of oversubscription in this architecture while potentially adopting a dragonfly-like network topology. This would also require fewer DPs worth of copper cables.
② Atomic Claim
在原文所述假設情境中，這種方案需要比目前 NVLink 7 更高 radix 的 switch，因為現有 NVLink 7 最大只提供 144 個 200G port。
- Epistemic Mode:
HYPOTHETICAL - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "MAXIMUM_SWITCH_RADIX",
"context_nodes": [
{
"id": "04_knowledge_base/200G",
"label": "200G"
}
],
"entity": {
"id": "04_knowledge_base/NVLink",
"label": "NVLink 7"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": "If all 288 GPUs are all-to-all; current NVLink 7 radix limitation",
"numeric_mentions": [
"144",
"200G"
],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"144",
"200G"
],
"value_text": "最大 radix 為 144 個 200G ports；NVL288 all-to-all 需要更高 radix switch。"
}
}④ Canonical Entity Mapping
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
在原文所述假設情境中，這種方案需要比目前 NVLink 7 更高 radix 的 switch，因為現有 NVLink 7 最大只提供 144 個 200G port。
V2 Semantic Frame Draft
{
"attribute": "MAXIMUM_SWITCH_RADIX",
"context_nodes": [
{
"id": "04_knowledge_base/200G",
"label": "200G"
}
],
"entity": {
"id": "04_knowledge_base/NVLink",
"label": "NVLink 7"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": "If all 288 GPUs are all-to-all; current NVLink 7 radix limitation",
"numeric_mentions": [
"144",
"200G"
],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"144",
"200G"
],
"value_text": "最大 radix 為 144 個 200G ports；NVL288 all-to-all 需要更高 radix switch。"
}
}V2 Revision Metadata Draft
{
"epistemic_mode": "HYPOTHETICAL",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。