clm_d91f42f4240c4347aa0a1c9122f5e6b7_r1

NIEK2-0091

① SA Source

• Source: 開啟完整 SA 文章
• Section: SRAM and Memory Hierarchy
• Line hint: 73

Context Before

LPU 3’s near reticle size die layout is very similar to LPU 1. a significant amount of area taken is up by the 500MB of on-chip SRAM, with a very small amount of area dedicated to MatMul cores that offer 1.2 PFLOPs of FP8 compute – a fraction of compute compared to Nvidia GPUs. This compares to LPU 1 with 230MB of SRAM and 750 TFLOPs of INT8, with the performance increase mostly driven by node migration from GF16 to SF4. As a single monolithic die, advanced packaging isn’t required.

One of the benefits of relying on SF4 is that it isn’t constrained like TSMC’s N3, which is putting a cap on accelerator production and is a key reason why the industry remains compute constrained. ↗ This is in addition to not having HBM which is also constrained ↗. This allows Nvidia to ramp production of the LPU without sacrificing or eating into their valuable TSMC allocation or HBM allocations, representing true incremental revenue and capacity that noone else can access.

Evidence

One of the technical innovations planned is hybrid bonded DRAM to extend on-chip memory with only a slight decrease in latency and bandwidth vs SRAM, but much higher performance compared to DRAM

Context After

Source: Nvidia, SemiAnalysis Accelerator Model ↗

② Atomic Claim

規劃中的一項技術創新，是透過 hybrid bonded DRAM 擴充片上記憶體；相較 SRAM 僅小幅犧牲延遲與頻寬，但效能明顯高於一般 DRAM。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "comparison_expression": "規劃中的一項技術創新，是透過 hybrid bonded DRAM 擴充片上記憶體；相較 SRAM 僅小幅犧牲延遲與頻寬，但效能明顯高於一般 DRAM。",
  "entities": [
    {
      "id": "04_knowledge_base/DRAM",
      "label": "DRAM"
    },
    {
      "id": "04_knowledge_base/SRAM",
      "label": "SRAM"
    }
  ],
  "frame_type": "COMPARISON",
  "metric": "BANDWIDTH",
  "operator": "GREATER_THAN",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [],
    "temporal_mentions": []
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
comparison_entity_0	DRAM	DRAM
comparison_entity_1	SRAM	SRAM

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。