clm_cfb5325a94a64ff9ba1a009f3d1ba0e7_r1

NIEK2-0227

① SA Source

• Source: 開啟完整 SA 文章
• Section: Oberon and Kyber Updates, Larger World Sizes Introduced, More Networking Updates
• Line hint: 281

Context Before

Each switch blade is also double in height vs the GTC 2025 prototype, with 6 NVLink 7 switches per switch blade, and 12 switch blades per rack, amounting to a total of 72 NVLink 7 switches per Kyber rack. The GPUs are connected all-to-all to the switch blades via 2 PCB midplanes or 1 midplane per canister.

Evidence

Kyber midplane PCB (GPU side)

Context After

For Rubin Ultra NVL144 Kyber, there will be no CPO used for scale up as we have told clients multiple times ↗, despite rumors from other analysts suggesting scale-up CPO introduction for Kyber. However, optics for NVLink are coming and will be progressively phased in. Scale-up CPO will first be used for the Rubin Ultra NVL 576 system to connect between 8 Oberon form factor racks, forming a two-layer all-to-all network. A copper backplane will still be used for scale-up networking within the racks however. This is still for low volume / testing purposes.

Moving back to the Kyber Rack, each Rubin Ultra logical GPU offers 14.4Tbit/s uni-di of scale-up bandwidth, using an 80DP connector (72 DPs used x 200Gbit/s bi-di channel = 14.4Tbit/s) per GPU for connectivity to the midplane board. Connecting all 144 GPUs in an all-to-all network will require 72 NVLink 7.0 Switch Chips running at 28.8Tbit/s uni-di of aggregate bandwidth each.

② Atomic Claim

此處所指為 Kyber midplane PCB 的 GPU 側。

• Epistemic Mode: ASSERTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "attribute": "UNSPECIFIED_ATTRIBUTE",
  "context_nodes": [
    {
      "id": "04_knowledge_base/Midplane",
      "label": "midplane"
    },
    {
      "id": "04_knowledge_base/PCB",
      "label": "PCB"
    },
    {
      "id": "04_knowledge_base/GPU",
      "label": "GPU"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/NVIDIA Kyber Rack",
    "label": "Kyber"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [],
    "value_text": "此處所指為 Kyber midplane PCB 的 GPU 側。"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	Kyber	04_knowledge_base/NVIDIA Kyber Rack
context_0	midplane	Midplane
context_1	PCB	PCB
context_2	GPU	GPU

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。