NIEK2-0064
① SA Source
- Source: 開啟完整 SA 文章
- Section:
SRAM and Memory Hierarchy - Line hint:
57
Context Before
SRAM and Memory Hierarchy
We have written about the role of SRAM in the memory hierarchy, but the quick recap is that SRAM is very fast (low latency and high bandwidth) but this comes at the expense of density and therefore cost.
Evidence
This is why Nvidia has decided to combine these architectures to get the best of both worlds: accelerate parts of decode that are more latency sensitive and are not as memory heavy on a low-latency SRAM-heavy chip like the LPU, while memory hungry attention is performed on GPUs that come with a lot of fast (but not SRAM fast) memory capacity
Context After
Source: SemiAnalysis
② Atomic Claim
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"comparison_expression": "decode 中記憶體需求較低的部分，可放在像 LPU 這類低延遲、以 SRAM 為主的晶片上加速。",
"entities": [
{
"id": "04_knowledge_base/Decode",
"label": "decode"
},
{
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
{
"id": "04_knowledge_base/SRAM",
"label": "SRAM"
}
],
"frame_type": "COMPARISON",
"metric": "LATENCY",
"operator": "LESS_THAN",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| comparison_entity_0 | decode | Decode |
| comparison_entity_1 | LPU | 04_knowledge_base/Groq LPU |
| comparison_entity_2 | SRAM | SRAM |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。