SA260324R-0034
① SA Source
- Source: 開啟完整 SA 文章
- Section:
LPU chip - Line hint:
41
Context Before
Source: Groq, SemiAnalysis
Evidence
The data flow and instruction flow design requires fine-grained pipelining to achieve high performance. Since LPU architecture makes computation deterministic, the compiler can aggressively schedule and overlap instructions to hide latency. The LPU’s use of high bandwidth SRAM and aggressive pipelining are the two main factors that enable LPU’s low latency.
Context After
LPU gen 1 was designed on a legacy Global Foundries 14nm process, with Marvell responsible for the chip’s physical design. This was a much more mature node compared to peers when it taped out in 2020, with the incumbent AI chip platforms mostly on TSMC’s N7 platform. This made sense for an early product focused on proving out Groq’s architecture and bringing its inference-centric design to market. The 14nm node was mature, relatively well understood, and suitable for an initial chip where architectural differentiation mattered more than pushing its silicon to the leading edge.
One of the selling points is that the chip can be manufactured and packaged entirely in the United States compared to their competitors being heavily reliant on the Asia semiconductor supply chain: logic and packaging in Taiwan, with HBM from Korea.
② Atomic Claim
由於 LPU 架構讓運算具備 deterministic 特性，compiler 可以更積極地排程並重疊 instructions，以隱藏 latency。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "DETERMINISM_COMPILER_SCHEDULING_IMPLICATION",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": "由於 LPU architecture makes computation deterministic",
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "deterministic computation 允許 compiler 積極排程與重疊 instructions 以隱藏 latency"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | LPU | 04_knowledge_base/Groq LPU |
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
由於 LPU 架構讓運算具備 deterministic 特性，compiler 可以更積極地排程並重疊 instructions，以隱藏 latency。
V2 Semantic Frame Draft
{
"attribute": "DETERMINISM_COMPILER_SCHEDULING_IMPLICATION",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": "由於 LPU architecture makes computation deterministic",
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "deterministic computation 允許 compiler 積極排程與重疊 instructions 以隱藏 latency"
}
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。