clm_b518405e7b3b46bab58a785b846bcbfe_r1

NIEK2-0136

① SA Source

• Source: 開啟完整 SA 文章
• Section: LPX Rack System
• Line hint: 147

Context Before

For LPUs, deploying a draft model or MTP layers is quite different from applying AFD. FFNs are stateless, while draft models and MTP layers require dynamic KV cache loading. Each FFN is around hundreds of megabytes, whereas draft models and MTP layers take up tens of gigabytes. To support this memory usage, LPUs can access up to 256 GB of DDR5 per Fabric Expansion Logic FPGAs on the LPX compute tray.

LPX Rack System

Evidence

Nvidia has displayed an LPX rack with 32 1U LPU compute trays with 2 Spectrum-X switches

Context After

Source: SemiAnalysis Accelerator Model ↗

② Atomic Claim

Nvidia 展示過一個 LPX 機櫃，內含 32 個 1U LPU compute trays 與 2 顆 Spectrum-X switches。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "COMPUTE_PERFORMANCE",
  "context_nodes": [
    {
      "id": "04_knowledge_base/Groq LPX",
      "label": "LPX"
    },
    {
      "id": "04_knowledge_base/Groq LPU",
      "label": "LPU"
    }
  ],
  "entity": {
    "id": "02_companies/NVDA",
    "label": "Nvidia"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "32",
      "1",
      "2"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "32",
      "1",
      "2"
    ],
    "value_text": "Nvidia 展示過一個 LPX 機櫃，內含 32 個 1U LPU compute trays 與 2 顆 Spectrum-X switches。"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	Nvidia	NVDA
context_0	LPX	04_knowledge_base/Groq LPX
context_1	LPU	04_knowledge_base/Groq LPU

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。