NIEK2-0033
① SA Source
- Source: 開啟完整 SA 文章
- Section:
LPU chip - Line hint:
41
Context Before
Source: Groq, SemiAnalysis
Evidence
Since LPU architecture makes computation deterministic, the compiler can aggressively schedule and overlap instructions to hide latency
Context After
LPU gen 1 was designed on a legacy Global Foundries 14nm process, with Marvell responsible for the chip’s physical design. This was a much more mature node compared to peers when it taped out in 2020, with the incumbent AI chip platforms mostly on TSMC’s N7 platform. This made sense for an early product focused on proving out Groq’s architecture and bringing its inference-centric design to market. The 14nm node was mature, relatively well understood, and suitable for an initial chip where architectural differentiation mattered more than pushing its silicon to the leading edge.
One of the selling points is that the chip can be manufactured and packaged entirely in the United States compared to their competitors being heavily reliant on the Asia semiconductor supply chain: logic and packaging in Taiwan, with HBM from Korea.
② Atomic Claim
由於 LPU 架構讓運算具有確定性，編譯器可以積極安排並重疊指令以隱藏延遲。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "LATENCY",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [],
"value_text": "由於 LPU 架構讓運算具有確定性，編譯器可以積極安排並重疊指令以隱藏延遲。"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | LPU | 04_knowledge_base/Groq LPU |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。