NIEK2-0327
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Feynman NVL1152 Networking Topologies - Line hint:
399
Context Before
Feynman NVL1152 Networking Topologies
Within each Feynman Kyber rack, we tentatively assume double the bandwidth per logical GPU and double the NVLink Switch bandwidth to 28.8T and 57.6T respectively. Though Jensen, in the Financial Q+A the day after the GTC Keynote, characterized NVL1152 as “all CPO”, the key technical blog outlining the new rack form factors ↗ only strictly referenced CPO for rack to rack interconnect. We will discuss the potential topography for both options.
Evidence
Context After

Source: SemiAnalysis
② Atomic Claim
若要用 copper interconnect 將 scale-up 頻寬加倍,NVIDIA 必須把每 lane 頻寬提升至 448Gbit/s uni-di,且配合 simultaneous bi-directional SerDes,讓每個實體 channel 同時承載 448G RX 與 448G TX。
- Epistemic Mode:
HYPOTHETICAL - Mapping Status:
PARTIAL
③ Semantic Frame
{
"comparison_expression": "若要用 copper interconnect 將 scale-up 頻寬加倍,NVIDIA 必須把每 lane 頻寬提升至 448Gbit/s uni-di,且配合 simultaneous bi-directional SerDes,讓每個實體 channel 同時承載 448G RX 與 448G TX。",
"entities": [
{
"id": "04_knowledge_base/Copper",
"label": "copper"
},
{
"id": "02_companies/NVDA",
"label": "NVIDIA"
},
{
"id": "04_knowledge_base/SerDes",
"label": "SerDes"
}
],
"frame_type": "COMPARISON",
"metric": "BANDWIDTH",
"operator": "MULTIPLE_OF",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"448Gb",
"448"
],
"temporal_mentions": []
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| comparison_entity_0 | copper | Copper |
| comparison_entity_1 | NVIDIA | NVDA |
| comparison_entity_2 | SerDes | SerDes |
⑤ Human Review
請在 Properties 逐項確認:
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。