clm_8260f545b4e04616ac78db155bbbcbd5_r2

SA260324R-0171

回到這篇 SA Coverage

① SA Source

• Source: 開啟完整 SA 文章
• Section: Intra-Tray Topology
• Line hint: 187

Context Before

Source: SemiAnalysis Networking Model ↗

Within each tray or node, all 16 LPUs are connected to each other in an all-to-all mesh. Each LPU module connects to the 15 other LPUs within the node with 4x100G of C2C bandwidth. Note that this ‘C2C’ is not related to NVLink, but Groq’s own scaleup fabric. These connections are all via PCB trace, which necessitates an extremely high spec PCB to support this routing density. This is why the belly-to-belly layout is used: it reduces the ‘X’ and ‘Y’ distance between all the LPUs and instead have routing go in the ‘Z’ dimension.

Evidence

The LPU also has 1x100G going to one FPGA, with each FPGA interfacing with 8 LPUs. The 2 FPGAs each have 8x PCIe Gen 5 going to the CPUs. The LPU needs to traverse through the FPGA to interface with the CPU as LPUs don’t have PCIe PHYs to interface directly.

Context After

Inter-node/Intra-rack

② Atomic Claim

2 顆 FPGA 各自都有 8× PCIe Gen 5 連到 CPU。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/FPGA",
        "label": "FPGA"
      },
      "role": "bridge"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCIe",
        "label": "PCIe"
      },
      "role": "protocol"
    },
    {
      "node": {
        "id": "04_knowledge_base/CPU",
        "label": "CPU"
      },
      "role": "destination"
    }
  ],
  "qualifiers": {
    "condition_text": "per FPGA",
    "numeric_mentions": [
      "2",
      "8x",
      "Gen 5"
    ],
    "temporal_mentions": []
  },
  "relation_type": "FPGA_TO_CPU_PCIE_CONNECTIVITY"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
bridge	FPGA	FPGA
protocol	PCIe	PCIe
destination	CPU	CPU

⑤ V2 Draft（需要修正時直接編輯）

Inline repair

只編輯以下三個 Draft 區塊。完成後將 review_action 設為 REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。

V2 Atomic Claim Draft

2 顆 FPGA 各自都有 8× PCIe Gen 5 連到 CPU。

V2 Semantic Frame Draft

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/FPGA",
        "label": "FPGA"
      },
      "role": "bridge"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCIe",
        "label": "PCIe"
      },
      "role": "protocol"
    },
    {
      "node": {
        "id": "04_knowledge_base/CPU",
        "label": "CPU"
      },
      "role": "destination"
    }
  ],
  "qualifiers": {
    "condition_text": "per FPGA",
    "numeric_mentions": [
      "2",
      "8x",
      "Gen 5"
    ],
    "temporal_mentions": []
  },
  "relation_type": "FPGA_TO_CPU_PCIE_CONNECTIVITY"
}

V2 Revision Metadata Draft

{
  "epistemic_mode": "ASSERTED",
  "mapping_status": "COMPLETE"
}

⑥ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。