SA260324R-0133
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Speculative Decoding - Line hint:
143
Context Before
Source: SemiAnalysis
Evidence
For LPUs, deploying a draft model or MTP layers is quite different from applying AFD. FFNs are stateless, while draft models and MTP layers require dynamic KV cache loading. Each FFN is around hundreds of megabytes, whereas draft models and MTP layers take up tens of gigabytes. To support this memory usage, LPUs can access up to 256 GB of DDR5 per Fabric Expansion Logic FPGAs on the LPX compute tray.
Context After
LPX Rack System
Let’s look at the LPX rack system, which has interesting details. Nvidia has displayed an LPX rack with 32 1U LPU compute trays with 2 Spectrum-X switches. This 32 tray 1U version that Nvidia has shown off at GTC is very close to Groq’s original server design before the acquisition. We believe that this server configuration is not the version that will be shipped in 3Q, with Nvidia implementing changes. Here, we will detail what we know about the actual production version. This was already detailed in the Accelerator model ↗.
② Atomic Claim
為了支援這種 memory usage，LPU 可透過 LPX compute tray 上每顆 Fabric Expansion Logic FPGA 存取最高 256GB 的 DDR5。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
"role": "compute_device"
},
{
"node": {
"id": "04_knowledge_base/DDR5",
"label": "DDR5"
},
"role": "memory"
},
{
"node": {
"id": "04_knowledge_base/FPGA",
"label": "FPGA"
},
"role": "fabric_expansion_logic"
},
{
"node": {
"id": "04_knowledge_base/Groq LPX",
"label": "LPX"
},
"role": "rack_system"
},
{
"node": {
"id": "04_knowledge_base/Compute Tray",
"label": "compute tray"
},
"role": "tray"
}
],
"qualifiers": {
"condition_text": "每顆 Fabric Expansion Logic FPGA",
"numeric_mentions": [
"256GB"
],
"temporal_mentions": []
},
"relation_type": "ACCESSES_DDR5_THROUGH_FPGA_ON_COMPUTE_TRAY"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| compute_device | LPU | 04_knowledge_base/Groq LPU |
| memory | DDR5 | DDR5 |
| fabric_expansion_logic | FPGA | FPGA |
| rack_system | LPX | 04_knowledge_base/Groq LPX |
| tray | compute tray | 04_knowledge_base/Compute Tray |
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
為了支援這種 memory usage，LPU 可透過 LPX compute tray 上每顆 Fabric Expansion Logic FPGA 存取最高 256GB 的 DDR5。
V2 Semantic Frame Draft
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
"role": "compute_device"
},
{
"node": {
"id": "04_knowledge_base/DDR5",
"label": "DDR5"
},
"role": "memory"
},
{
"node": {
"id": "04_knowledge_base/FPGA",
"label": "FPGA"
},
"role": "fabric_expansion_logic"
},
{
"node": {
"id": "04_knowledge_base/Groq LPX",
"label": "LPX"
},
"role": "rack_system"
},
{
"node": {
"id": "04_knowledge_base/Compute Tray",
"label": "compute tray"
},
"role": "tray"
}
],
"qualifiers": {
"condition_text": "每顆 Fabric Expansion Logic FPGA",
"numeric_mentions": [
"256GB"
],
"temporal_mentions": []
},
"relation_type": "ACCESSES_DDR5_THROUGH_FPGA_ON_COMPUTE_TRAY"
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。