SA260324R-0082
① SA Source
- Source: 開啟完整 SA 文章
- Section:
SRAM and Memory Hierarchy - Line hint:
71
Context Before
Source: Nvidia
LPU 3’s near reticle size die layout is very similar to LPU 1. a significant amount of area taken is up by the 500MB of on-chip SRAM, with a very small amount of area dedicated to MatMul cores that offer 1.2 PFLOPs of FP8 compute – a fraction of compute compared to Nvidia GPUs. This compares to LPU 1 with 230MB of SRAM and 750 TFLOPs of INT8, with the performance increase mostly driven by node migration from GF16 to SF4. As a single monolithic die, advanced packaging isn’t required.
Evidence
One of the benefits of relying on SF4 is that it isn’t constrained like TSMC’s N3, which is putting a cap on accelerator production and is a key reason why the industry remains compute constrained. ↗ This is in addition to not having HBM which is also constrained ↗. This allows Nvidia to ramp production of the LPU without sacrificing or eating into their valuable TSMC allocation or HBM allocations, representing true incremental revenue and capacity that noone else can access.
Context After
Since Nvidia has taken over, the next generation LP40 will be fabricated on TSMC N3P and use CoWoS-R, and Nvidia will contribute more of their own IP such as supporting the NVLink protocol rather than Groq’s C2C. This will be the first LPU to be extremely co-designed alongside the Feynman platform. Groq’s original plans for LPU Gen 4 was also with TSMC and Alchip as the back-end design partner. Alchip’s involvement is now redundant with Nvidia able to perform backend design on their own. One of the technical innovations planned is hybrid bonded DRAM to extend on-chip memory with only a slight decrease in latency and bandwidth vs SRAM, but much higher performance compared to DRAM. SK Hynix was tapped as the supplier of the DRAM to be used for the 3D stacking. All of this and more was detailed long ago in the Accelerator model ↗.
② Atomic Claim
SemiAnalysis characterizes the LPUs’ use of available SF4 capacity as incremental capacity unavailable to competitors relying on constrained TSMC/HBM allocations.
- Epistemic Mode:
ASSERTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"frame_type": "CLAIM_ONLY",
"qualifiers": {
"condition_text": "承接前一 claim 的 LPU incremental capacity",
"numeric_mentions": [],
"temporal_mentions": []
},
"reason": "此句是上一條 incremental capacity 敘述的續句，沒有獨立明示 canonical entity。",
"statement": "SemiAnalysis characterizes the LPUs’ use of available SF4 capacity as incremental capacity unavailable to competitors relying on constrained TSMC/HBM allocations."
}④ Canonical Entity Mapping
- 此
CLAIM_ONLYrevision 沒有 canonical Entity mapping。
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
SemiAnalysis characterizes the LPUs’ use of available SF4 capacity as incremental capacity unavailable to competitors relying on constrained TSMC/HBM allocations.
V2 Semantic Frame Draft
{
"frame_type": "CLAIM_ONLY",
"qualifiers": {
"condition_text": "承接前一 claim 的 LPU incremental capacity",
"numeric_mentions": [],
"temporal_mentions": []
},
"reason": "此句是上一條 incremental capacity 敘述的續句，沒有獨立明示 canonical entity。",
"statement": "SemiAnalysis characterizes the LPUs’ use of available SF4 capacity as incremental capacity unavailable to competitors relying on constrained TSMC/HBM allocations."
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "PARTIAL"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。