NIEK2-0151
① SA Source
- Source: 開啟完整 SA 文章
- Section:
LPX Compute Tray - Line hint:
167
Context Before
Source: SemiAnalysis Networking Model ↗
Evidence
Context After
Second, the LPUs also traverse through the FPGAs to reach the host CPU, with the FPGAs converting C2C to PCIe to the CPU.
Third, the FPGAs are connected to the backplane to talk to other FPGAs in the node, we believe this is to help manage control flow and timing of all the LPUs. The FPGAs also bring extra system DRAM of up to 256GB each. This pool of memory can be used for KVCache if the user wants the entire decode process served by the LPX.
② Atomic Claim
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"additional_nodes": [
{
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
}
],
"frame_type": "RELATION",
"object": {
"id": "04_knowledge_base/GPU",
"label": "GPUs"
},
"predicate": "CONNECTS_TO",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"subject": {
"id": "04_knowledge_base/Decode",
"label": "decode"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| subject | decode | Decode |
| object | GPUs | GPU |
| additional_0 | LPU | 04_knowledge_base/Groq LPU |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。