SA260324R-0151
① SA Source
- Source: 開啟完整 SA 文章
- Section:
LPX Compute Tray - Line hint:
169
Context Before
Source: SemiAnalysis Networking Model ↗
Something interesting about the system is the important role the FPGAs play. Nvidia refers to the FPGAs as “Fabric Expansion Logic” which serves multiple purposes. First, they act as a NIC which converts the LPU’s C2C protocol into Ethernet to connect to the Spectrum-X based ethernet scale-out fabric. It is this scale-out fabric through which the LPUs connect to GPUs in the decode system.
Evidence
Context After
Third, the FPGAs are connected to the backplane to talk to other FPGAs in the node, we believe this is to help manage control flow and timing of all the LPUs. The FPGAs also bring extra system DRAM of up to 256GB each. This pool of memory can be used for KVCache if the user wants the entire decode process served by the LPX.
On the front panel there are 8 x OSFP cages for cross-rack C2C, while there will be 2 cages (likely QSFP-DD) that goes to the Spectrum-switches that is used to connect the LPUs and the GPUs for the disaggregated decode system. We will share more about this when we describe the network.
② Atomic Claim
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
"role": "source_device"
},
{
"node": {
"id": "04_knowledge_base/FPGA",
"label": "FPGA"
},
"role": "protocol_bridge"
},
{
"node": {
"id": "04_knowledge_base/CPU",
"label": "CPU"
},
"role": "destination_device"
},
{
"node": {
"id": "04_knowledge_base/Chip-to-Chip Interconnect",
"label": "C2C"
},
"role": "source_protocol"
},
{
"node": {
"id": "04_knowledge_base/PCIe",
"label": "PCIe"
},
"role": "destination_protocol"
}
],
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"relation_type": "HOST_CPU_CONNECTIVITY_PATH"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| source_device | LPU | 04_knowledge_base/Groq LPU |
| protocol_bridge | FPGA | FPGA |
| destination_device | CPU | CPU |
| source_protocol | C2C | 04_knowledge_base/Chip-to-Chip Interconnect |
| destination_protocol | PCIe | PCIe |
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
其次，LPU 也會經過 FPGA 才能連到 host CPU；FPGA 會把 C2C 轉成 PCIe 再連至 CPU。
V2 Semantic Frame Draft
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
"role": "source_device"
},
{
"node": {
"id": "04_knowledge_base/FPGA",
"label": "FPGA"
},
"role": "protocol_bridge"
},
{
"node": {
"id": "04_knowledge_base/CPU",
"label": "CPU"
},
"role": "destination_device"
},
{
"node": {
"id": "04_knowledge_base/Chip-to-Chip Interconnect",
"label": "C2C"
},
"role": "source_protocol"
},
{
"node": {
"id": "04_knowledge_base/PCIe",
"label": "PCIe"
},
"role": "destination_protocol"
}
],
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"relation_type": "HOST_CPU_CONNECTIVITY_PATH"
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。