SA260324R-0176
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Inter-node/Intra-rack - Line hint:
195
Context Before
Source: SemiAnalysis Networking Model ↗
Evidence
Each LPU connects to one LPU from each of the 15 other nodes in the server. Each of these inter-node links is 2x100G so there are 15x2x100G inter-node links coming out of each LPU. These inter-node links are via a copper cable backplane. In addition, each FPGA also connects to an FPGA in every other node at either 25G or 50G per link for 15x25G/50G. This also goes through the backplane. This means that each node has 16 x 15 x 2 lanes for inter-node C2C and 2 x 15 lanes for inter-node FPGA which is a total of 510 lanes or 1020 differential pairs (for Rx and Tx). Therefore, the backplane is 16 x 1020/2 = 8,160 differential pairs – we divide by 2 as each device Tx channel is a corresponding device’s Rx channel.
Context After
Inter-rack
② Atomic Claim
此外，每顆 FPGA 都會連到其他每個 node 中的一顆 FPGA，每條 link 為 25G 或 50G，合計為 15×25G／50G。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "INTER_NODE_CONNECTIVITY",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/FPGA",
"label": "FPGA"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": "inter-node FPGA links",
"numeric_mentions": [
"25G",
"50G",
"15x25G/50G"
],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"25G",
"50G",
"15x25G/50G"
],
"value_text": "每顆 FPGA 連到其他每個 node 的 FPGA，每條 link 25G 或 50G，合計 15×25G／50G。"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | FPGA | FPGA |
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
此外，每顆 FPGA 都會連到其他每個 node 中的一顆 FPGA，每條 link 為 25G 或 50G，合計為 15×25G／50G。
V2 Semantic Frame Draft
{
"attribute": "INTER_NODE_CONNECTIVITY",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/FPGA",
"label": "FPGA"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": "inter-node FPGA links",
"numeric_mentions": [
"25G",
"50G",
"15x25G/50G"
],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"25G",
"50G",
"15x25G/50G"
],
"value_text": "每顆 FPGA 連到其他每個 node 的 FPGA，每條 link 25G 或 50G，合計 15×25G／50G。"
}
}V2 Revision Metadata Draft
{
"epistemic_mode": "ASSERTED",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。