clm_6a953680e2f240c98bd922e3000c816b_r1

NIEK2-0163

① SA Source

• Source: 開啟完整 SA 文章
• Section: Intra-Tray Topology
• Line hint: 185

Context Before

Source: SemiAnalysis Networking Model ↗

Evidence

Each LPU module connects to the 15 other LPUs within the node with 4x100G of C2C bandwidth

Context After

The LPU also has 1x100G going to one FPGA, with each FPGA interfacing with 8 LPUs. The 2 FPGAs each have 8x PCIe Gen 5 going to the CPUs. The LPU needs to traverse through the FPGA to interface with the CPU as LPUs don’t have PCIe PHYs to interface directly.

Inter-node/Intra-rack

② Atomic Claim

每顆 LPU module 會以 4×100G C2C 頻寬，連接 node 內其他 15 顆 LPU。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "comparison_expression": "每顆 LPU module 會以 4×100G C2C 頻寬，連接 node 內其他 15 顆 LPU。",
  "entities": [
    {
      "id": "04_knowledge_base/Groq LPU",
      "label": "LPU"
    },
    {
      "id": "04_knowledge_base/100G",
      "label": "100G"
    },
    {
      "id": "04_knowledge_base/Chip-to-Chip Interconnect",
      "label": "C2C"
    }
  ],
  "frame_type": "COMPARISON",
  "metric": "BANDWIDTH",
  "operator": "MULTIPLE_OF",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "4×",
      "100",
      "15"
    ],
    "temporal_mentions": []
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
comparison_entity_0	LPU	04_knowledge_base/Groq LPU
comparison_entity_1	100G	100G
comparison_entity_2	C2C	04_knowledge_base/Chip-to-Chip Interconnect

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。