clm_64f05c4383324a00a3463733b6dd2504_r1

NIEK2-0160

① SA Source

• Source: 開啟完整 SA 文章
• Section: LPU Network
• Line hint: 177

Context Before

On the front panel there are 8 x OSFP cages for cross-rack C2C, while there will be 2 cages (likely QSFP-DD) that goes to the Spectrum-switches that is used to connect the LPUs and the GPUs for the disaggregated decode system. We will share more about this when we describe the network.

LPU Network

Evidence

For C2C within the rack Nvidia announced a total of 640TB/s of scale up bandwidth per rack which comes from 256 LPUs x 90 lanes x 112Gbps/8 x 2 directions = 645TB/s

Context After

Intra-Tray Topology

② Atomic Claim

對機櫃內 C2C 而言，Nvidia 宣稱每櫃總 scale-up 頻寬為 640TB/s；依 256 LPUs × 90 lanes × 112Gbps ÷ 8 × 2 directions 計算則為 645TB/s。

• Epistemic Mode: ATTRIBUTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "comparison_expression": "對機櫃內 C2C 而言，Nvidia 宣稱每櫃總 scale-up 頻寬為 640TB/s；依 256 LPUs × 90 lanes × 112Gbps ÷ 8 × 2 directions 計算則為 645TB/s。",
  "entities": [
    {
      "id": "04_knowledge_base/Chip-to-Chip Interconnect",
      "label": "C2C"
    },
    {
      "id": "02_companies/NVDA",
      "label": "Nvidia"
    }
  ],
  "frame_type": "COMPARISON",
  "metric": "BANDWIDTH",
  "operator": "MULTIPLE_OF",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "640TB/s",
      "256",
      "90",
      "112Gbps",
      "8 ×",
      "2",
      "645TB/s"
    ],
    "temporal_mentions": []
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
comparison_entity_0	C2C	04_knowledge_base/Chip-to-Chip Interconnect
comparison_entity_1	Nvidia	NVDA

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。