NIEK2-0169
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Intra-Tray Topology - Line hint:
187
Context Before
Source: SemiAnalysis Networking Model ↗
Within each tray or node, all 16 LPUs are connected to each other in an all-to-all mesh. Each LPU module connects to the 15 other LPUs within the node with 4x100G of C2C bandwidth. Note that this ‘C2C’ is not related to NVLink, but Groq’s own scaleup fabric. These connections are all via PCB trace, which necessitates an extremely high spec PCB to support this routing density. This is why the belly-to-belly layout is used: it reduces the ‘X’ and ‘Y’ distance between all the LPUs and instead have routing go in the ‘Z’ dimension.
Evidence
Context After
Inter-node/Intra-rack
② Atomic Claim
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/PCIe",
"label": "PCIe"
},
"role": "endpoint_or_system"
},
{
"node": {
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
"role": "connected_entity"
},
{
"node": {
"id": "04_knowledge_base/FPGA",
"label": "FPGA"
},
"role": "connected_entity"
},
{
"node": {
"id": "04_knowledge_base/CPU",
"label": "CPU"
},
"role": "connected_entity"
}
],
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"relation_type": "CONNECTS_TO"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| endpoint_or_system | PCIe | PCIe |
| connected_entity | LPU | 04_knowledge_base/Groq LPU |
| connected_entity | FPGA | FPGA |
| connected_entity | CPU | CPU |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。