clm_5af1c9f06ee9459690e0f21c6361d3f3_r1

NIEK2-0165

① SA Source

• Source: 開啟完整 SA 文章
• Section: Intra-Tray Topology
• Line hint: 185

Context Before

Source: SemiAnalysis Networking Model ↗

Evidence

These connections are all via PCB trace, which necessitates an extremely high spec PCB to support this routing density

Context After

The LPU also has 1x100G going to one FPGA, with each FPGA interfacing with 8 LPUs. The 2 FPGAs each have 8x PCIe Gen 5 going to the CPUs. The LPU needs to traverse through the FPGA to interface with the CPU as LPUs don’t have PCIe PHYs to interface directly.

Inter-node/Intra-rack

② Atomic Claim

這些連線全部透過 PCB traces，因此必須使用極高規格的 PCB 才能支援如此高的 routing 密度。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "SUPPORT_STATUS",
  "context_nodes": [],
  "entity": {
    "id": "04_knowledge_base/PCB",
    "label": "PCB"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [],
    "value_text": "這些連線全部透過 PCB traces，因此必須使用極高規格的 PCB 才能支援如此高的 routing 密度。"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	PCB	PCB

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。