clm_4ab38937c95a4364a9c323e22b0bf18a_r1

NIEK2-0296

① SA Source

• Source: 開啟完整 SA 文章
• Section: CMX
• Line hint: 367

Context Before

CMX

CMX is NVIDIA’s context memory storage platform. CMX addresses a growing bottleneck in modern inference infrastructure: the rapid expansion of KV Cache required to support long-context and agentic workloads.

Evidence

Host DRAM extends beyond HBM capacity with an additional tier of cache

Context After

NVIDIA introduced a “new” intermediate storage “tier G3.5” within the inference memory hierarchy at CES in January. Tier G3.5 NVMe sits in between tier G3 DRAM and tier G4 shared storage (also NVMe, or SATA/SAS SSD, or HDD). Previously referred to as ICMS (Inference Context Memory Storage) and now branded as the CMX platform, this is just another re-brand of storage servers attached to compute servers via Bluefield NICs. The only difference from NVMe architectures is the swap from Connect-X NICs to Bluefield NICs.

② Atomic Claim

Host DRAM 可在 HBM 之外增加一層 cache，進一步擴充容量。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "CAPACITY",
  "context_nodes": [
    {
      "id": "04_knowledge_base/HBM",
      "label": "HBM"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/DRAM",
    "label": "DRAM"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [],
    "value_text": "Host DRAM 可在 HBM 之外增加一層 cache，進一步擴充容量。"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	DRAM	DRAM
context_0	HBM	HBM

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。