SA260324R-0185
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Inter-rack - Line hint:
203
Context Before
Source: SemiAnalysis Networking Model ↗
Evidence
Lastly, there is the inter-rack C2C. Each LPU has 4x100G lanes that go to the OSFP cages to connect LPUs across 4 racks. There are various configurations that can be used for this inter-rack scale up. One option is 4x100G from each LPU going to one OSFP cage, each OSFP escaping 800G of C2C from 2 LPUs. However, for greater fan out the preferred configuration seems to be each 100G lane from the LPU going to 4 individual cages, with each cage escaping 800G of C2C from 8 LPUs. In terms of how the racks are networked together it appears to be a daisy chain configuration, with each Node0 connected to 2 other Node 0. This can all be achieved within the reach of 100G AECs, though optics can be used if necessary.
Context After
Nvidia’s CPO Roadmap
NVIDIA revealed its CPO Roadmap at the GTC Keynote 2026, with Jensen following up with additional commentary in the Financial Analyst Q+A meeting held the following day. Though many had their hopes up for CPO to be used for scale-up within the rack for Rubin Ultra Kyber, Nvidia’s focus was instead on using CPO to enable larger world size compute systems.
② Atomic Claim
若要更大的 fan-out，偏好的 configuration 看起來是讓 LPU 的每條 100G lane 分別連到 4 個 cage；每個 cage 會從 8 顆 LPU 對外導出 800G 的 C2C。
- Epistemic Mode:
INFERRED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/100G",
"label": "100G"
},
"role": "lane_rate"
},
{
"node": {
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
"role": "accelerator"
},
{
"node": {
"id": "04_knowledge_base/800G",
"label": "800G"
},
"role": "aggregate_bandwidth"
},
{
"node": {
"id": "04_knowledge_base/Chip-to-Chip Interconnect",
"label": "C2C"
},
"role": "protocol"
}
],
"qualifiers": {
"condition_text": "cage 類型承接前文 OSFP，但本 fragment 未再次 canonical link; LPX inter-rack C2C; greater-fanout option; seems preferred",
"numeric_mentions": [
"100G",
"4",
"8",
"800G"
],
"temporal_mentions": []
},
"relation_type": "HIGH_FANOUT_INTERRACK_CONFIGURATION"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| lane_rate | 100G | 100G |
| accelerator | LPU | 04_knowledge_base/Groq LPU |
| aggregate_bandwidth | 800G | 800G |
| protocol | C2C | 04_knowledge_base/Chip-to-Chip Interconnect |
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
若要更大的 fan-out，偏好的 configuration 看起來是讓 LPU 的每條 100G lane 分別連到 4 個 cage；每個 cage 會從 8 顆 LPU 對外導出 800G 的 C2C。
V2 Semantic Frame Draft
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/100G",
"label": "100G"
},
"role": "lane_rate"
},
{
"node": {
"id": "04_knowledge_base/Groq LPU",
"label": "LPU"
},
"role": "accelerator"
},
{
"node": {
"id": "04_knowledge_base/800G",
"label": "800G"
},
"role": "aggregate_bandwidth"
},
{
"node": {
"id": "04_knowledge_base/Chip-to-Chip Interconnect",
"label": "C2C"
},
"role": "protocol"
}
],
"qualifiers": {
"condition_text": "cage 類型承接前文 OSFP，但本 fragment 未再次 canonical link; LPX inter-rack C2C; greater-fanout option; seems preferred",
"numeric_mentions": [
"100G",
"4",
"8",
"800G"
],
"temporal_mentions": []
},
"relation_type": "HIGH_FANOUT_INTERRACK_CONFIGURATION"
}V2 Revision Metadata Draft
{
"epistemic_mode": "INFERRED",
"mapping_status": "PARTIAL"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。