NIEK2-0152

① SA Source

Context Before

Source: SemiAnalysis Networking Model

Something interesting about the system is the important role the FPGAs play. Nvidia refers to the FPGAs as “Fabric Expansion Logic” which serves multiple purposes. First, they act as a NIC which converts the LPU’s C2C protocol into Ethernet to connect to the Spectrum-X based ethernet scale-out fabric. It is this scale-out fabric through which the LPUs connect to GPUs in the decode system.

Evidence

Second, the LPUs also traverse through the FPGAs to reach the host CPU, with the FPGAs converting C2C to PCIe to the CPU

Context After

Third, the FPGAs are connected to the backplane to talk to other FPGAs in the node, we believe this is to help manage control flow and timing of all the LPUs. The FPGAs also bring extra system DRAM of up to 256GB each. This pool of memory can be used for KVCache if the user wants the entire decode process served by the LPX.

On the front panel there are 8 x OSFP cages for cross-rack C2C, while there will be 2 cages (likely QSFP-DD) that goes to the Spectrum-switches that is used to connect the LPUs and the GPUs for the disaggregated decode system. We will share more about this when we describe the network.

② Atomic Claim

第二,LPU 也必須經由 FPGAs 連到 host CPU,由 FPGAsC2C 轉換成 PCIe 後再連至 CPU

  • Epistemic Mode: ASSERTED
  • Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/FPGA",
        "label": "FPGAs"
      },
      "role": "endpoint_or_system"
    },
    {
      "node": {
        "id": "04_knowledge_base/CPU",
        "label": "CPU"
      },
      "role": "connected_entity"
    },
    {
      "node": {
        "id": "04_knowledge_base/Chip-to-Chip Interconnect",
        "label": "C2C"
      },
      "role": "connected_entity"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCIe",
        "label": "PCIe"
      },
      "role": "connected_entity"
    }
  ],
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "relation_type": "CONNECTS_TO"
}

④ Canonical Entity Mapping

RoleSurface LabelCanonical Target
endpoint_or_systemFPGAsFPGA
connected_entityCPUCPU
connected_entityC2C04_knowledge_base/Chip-to-Chip Interconnect
connected_entityPCIePCIe

⑤ Human Review

請在 Properties 逐項確認:

  • 原文 → Atomic Claim 是否忠實
  • Atomic Claim → Semantic Frame 是否忠實
  • Canonical Entity mapping 是否正確
  • Epistemic mode 是否保留原文語氣
  • 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。