SA-COV-SA-144
① SA Source
- Source: 開啟完整 SA 文章
- Section:
LPU chip - Line hint:
37
Context Before
Groq’s first and only publicly announced LPU architecture was detailed in their ISCA 2020 paper. Unlike typical hardware architectures connecting many general-purpose cores, Groq re-organized the architecture into groups of single-purpose units connecting to other groups of different purposes, and they named the groups “slices.” Between functional units are streaming registers, scratchpad SRAM for functional units to pass data to each other. Groq opted for single-level scratchpad SRAM instead of multi-level memory hierarchy to make the hardware execution deterministic.
Concretely, LPU architecture has VXM slices for vector operations, MEM slices for loading/storing data, SXM slices for tensor shape manipulation, and MXM slices for performing matrix multiplication. Spatially, the slices are laid out horizontally, allowing the data to stream horizontally. Within a slice, instructions are pumped vertically across units. Conceptually, LPU resembles a systolic array that pumps instructions vertically and data horizontally.
Evidence
Context After
Source: Groq, SemiAnalysis
The data flow and instruction flow design requires fine-grained pipelining to achieve high performance. Since LPU architecture makes computation deterministic, the compiler can aggressively schedule and overlap instructions to hide latency. The LPU’s use of high bandwidth SRAM and aggressive pipelining are the two main factors that enable LPU’s low latency.
② Atomic Claim
The Groq streaming architecture diagram labels 144 instruction-dispatch paths.
- Epistemic Mode:
ATTRIBUTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "ILLUSTRATED_INSTRUCTION_DISPATCH_PATHS",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/Groq LPU",
"label": "Groq LPU"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"144"
],
"value_text": "144"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | Groq LPU | 04_knowledge_base/Groq LPU |
⑤ V2 Draft（需要修正時直接編輯）
Inline repair
只編輯以下三個 Draft 區塊。完成後將
review_action設為REQUEST_REPAIR，再手動執行 Repair Preview。
執行腳本前，Draft 不會寫入 Claim Store 或 Graph。
V2 Atomic Claim Draft
The Groq streaming architecture diagram labels 144 instruction-dispatch paths.
V2 Semantic Frame Draft
{
"attribute": "ILLUSTRATED_INSTRUCTION_DISPATCH_PATHS",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/Groq LPU",
"label": "Groq LPU"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"144"
],
"value_text": "144"
}
}V2 Revision Metadata Draft
{
"epistemic_mode": "ATTRIBUTED",
"mapping_status": "COMPLETE"
}⑥ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。