VR2R-0701_r1

VR2R-0701

① SA Source

• Source: 開啟完整 SA 文章
• Section: VR NVL72 TCO: BoM and Power Budget Analysis
• Line hint: 607

Context Before

However, one advantage for Nvidia’s VR SOCAMM option is that NVIDIA directly procures memory, allowing them to negotiate long-term agreements, volume-preferential terms with memory suppliers and most importantly, VVIP pricing. We think this will shield end customers from spikes in memory costs as we outline in our AI server apocalypse note, and is another example of how, as the Central Bank of AI, Nvidia is effectively hedging DRAM prices for all of its customers.

Evidence

By contrast, AMD is much more exposed to DRAM price increases as it has about double the amount of DRAM, with about 55 TB per rack of LPDDR5 and 55 TB per rack of DDR5.

Context After

For AMD’s Helios rack scale system, AMD sells the GPU/board and does procure the LPDDR5 memory, but it does not procure DDR5 DRAM for rack compute trays; rack assemblers/ODMs source and integrate DDR5 memory. This leaves buyers of AMD’s racks more exposed because AMD is only able to potentially “hedge” the LPDDR5 portion via long-term contracts leaving the DDR5 portion completely exposed. Having double the DRAM content also nearly doubles the overall exposure.

② Atomic Claim

相較之下，AMD 對 DRAM 漲價的曝險更高，因為其 DRAM 容量約為兩倍；每個 rack 約有 55 TB LPDDR5 與 55 TB DDR5。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "02_companies/AMD",
        "label": "AMD"
      },
      "role": "vendor"
    },
    {
      "node": {
        "id": "04_knowledge_base/DRAM",
        "label": "DRAM"
      },
      "role": "memory"
    },
    {
      "node": {
        "id": "04_knowledge_base/LPDDR5",
        "label": "LPDDR5"
      },
      "role": "memory_type"
    },
    {
      "node": {
        "id": "04_knowledge_base/DDR5",
        "label": "DDR5"
      },
      "role": "memory_type"
    }
  ],
  "qualifiers": {
    "condition_text": "per rack memory content",
    "numeric_mentions": [
      "2x",
      "55 TB",
      "55 TB"
    ],
    "temporal_mentions": []
  },
  "relation_type": "AMD_HIGHER_DRAM_PRICE_EXPOSURE_FROM_MEMORY_CONTENT"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
vendor	AMD	AMD
memory	DRAM	DRAM
memory_type	LPDDR5	LPDDR5
memory_type	DDR5	DDR5

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。