VR2R-0638_r1

VR2R-0638

① SA Source

• Source: 開啟完整 SA 文章
• Section: Ethernet-Based Cluster Deployments
• Line hint: 548

Context Before

Recall that the SN6800 contains four Switch ASICs in a multi-plane configuration connected to ports via an integrated fiber shuffle, delivering 409.6T aggregate bandwidth, while the SN6810 uses one Switch ASIC, but without any integrated fiber shuffle, to deliver 102.4T aggregate bandwidth.

Evidence

Large-scale cluster deployments where cluster sizes exceed 100k GPUs typically utilize multi-plane network architectures because single-plane network architectures do not have enough logical ports at current switch generations to support larger networks without resorting to a high number of switch layers of 3 or more layers.

Context After

Recall from above that a Vera Rubin NVL72 cluster built with Q3400-X800 switches at 1.6T logical ports per GPU cannot scale beyond the maximum cluster size of 93,312 GPUs. Even if future switch generations continue to double the maximum possible switching capacity per switch box, the per GPU bandwidth is also expected to double, which means that the effective logical port count in a cluster network is unlikely to change.

② Atomic Claim

超過 10 萬顆 GPU 的大型 cluster 通常採用 multi-plane network architecture，因為現世代 switch 的 single-plane architecture 沒有足夠 logical ports；若要支援更大 network，否則通常必須增加到 3 層以上的 switch layers。

• Epistemic Mode: ASSERTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "attribute": "LARGE_CLUSTER_NETWORK_ARCHITECTURE_REQUIREMENT",
  "context_nodes": [],
  "entity": {
    "id": "04_knowledge_base/GPU",
    "label": "GPU"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": "multi-plane architecture and logical ports are plain-text topology concepts",
    "numeric_mentions": [
      "100k",
      "3"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "100k",
      "3"
    ],
    "value_text": "clusters above 100k GPUs typically use multi-plane networking because current single-plane switch radix is insufficient without three or more switch layers."
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	GPU	GPU

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。