VR2R-0590

① SA Source

Context Before

The Quantum X800-Q3400 is logically a multi-plane switch combining 4 Quantum-3 ASICs into a single switch box. This multi-plane “topology” is abstracted away and as far as network engineers are concerned, the Q3400 is a single switch with 144 ports—or a “little boy” switch.

Evidence

The InfiniBand architecture for the HGX Rubin NVL8 server is therefore effectively a single-plane, 8-rail network consisting of one 800G uplink from each HGX Rubin NVL8 GPU to a leaf switch.

Context After

For the Vera Rubin NVL72 deployment however, there are two 800G OSFP cages per GPU for a total of 1.6T per GPU bandwidth. Having two 800G logical ports per GPU is advantageous because it allows multi-plane network deployments without complex fiber management—by splitting one logical GPU two ways to two different leaf switches. As such, larger network clusters can be built with two 800G logical ports than if only one 1.6T logical port were used.

② Atomic Claim

因此,HGX Rubin NVL8 server 的 InfiniBand architecture,實際上相當於 single-plane、8-rail network;每顆 HGX Rubin NVL8 GPU 各有一條 800G uplink 連到 leaf switch。

  • Epistemic Mode: INFERRED
  • Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/InfiniBand",
        "label": "InfiniBand"
      },
      "role": "fabric"
    },
    {
      "node": {
        "id": "04_knowledge_base/HGX",
        "label": "HGX"
      },
      "role": "platform"
    },
    {
      "node": {
        "id": "04_knowledge_base/Vera Rubin",
        "label": "Rubin"
      },
      "role": "processor"
    },
    {
      "node": {
        "id": "04_knowledge_base/GPU",
        "label": "GPU"
      },
      "role": "processor_type"
    }
  ],
  "qualifiers": {
    "condition_text": "inferred architecture; leaf switch is plain text",
    "numeric_mentions": [
      "1",
      "8",
      "800G"
    ],
    "temporal_mentions": []
  },
  "relation_type": "HGX_RUBIN_NVL8_INFINIBAND_SINGLE_PLANE_EIGHT_RAIL"
}

④ Canonical Entity Mapping

RoleSurface LabelCanonical Target
fabricInfiniBandInfiniBand
platformHGXHGX
processorRubin04_knowledge_base/Vera Rubin
processor_typeGPUGPU

⑤ Human Review

請在 Properties 逐項確認:

  • 原文 → Atomic Claim 是否忠實
  • Atomic Claim → Semantic Frame 是否忠實
  • Canonical Entity mapping 是否正確
  • Epistemic mode 是否保留原文語氣
  • 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。