VR2R-0573_r1

VR2R-0573

① SA Source

• Source: 開啟完整 SA 文章
• Section: Scale-Up Network - NVLink 6
• Line hint: 476

Context Before

The HGX Rubin NVL8 server consists of eight 800G CX-9 NIC packages—one NIC per GPU—which means that the scale-out bandwidth does not increase from its predecessor, the HGX B300 server. The Vera Rubin NVL72 deployment on the other hand doubles the per GPU scale-out bandwidth to 1.6T, but not by doubling the bandwidth per NIC.

Evidence

Rather, the “1.6T NIC” attached to each Rubin chip is comprised of two 800G CX-9 packages that is connected to the Vera CPU by PCIe Gen 6.0 lanes.

Context After

Each compute tray on the VR NVL72 has eight 800G CX-9 NICs, but there are two possibilities for the number of OSFP cages—either one 1.6T OSFP cage per GPU for a total of 4 per compute tray, or two 800G OSFP cages per GPU for a total of 8 cages per compute tray. We think that the latter would be the more popular deployment assumption.

② Atomic Claim

每顆 Rubin chip 所連接的「1.6T NIC」其實由 2 個 800G CX-9 packages 組成，並透過 PCIe Gen 6.0 lanes 連接到 Vera CPU。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/Vera Rubin",
        "label": "Rubin"
      },
      "role": "processor"
    },
    {
      "node": {
        "id": "04_knowledge_base/NIC",
        "label": "NIC"
      },
      "role": "network_interface"
    },
    {
      "node": {
        "id": "04_knowledge_base/ConnectX-9",
        "label": "CX-9"
      },
      "role": "nic_package"
    },
    {
      "node": {
        "id": "04_knowledge_base/NVIDIA Vera CPU",
        "label": "Vera CPU"
      },
      "role": "host_cpu"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCIe",
        "label": "PCIe Gen 6.0"
      },
      "role": "host_link"
    }
  ],
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "1.6T",
      "2",
      "800G",
      "6.0"
    ],
    "temporal_mentions": []
  },
  "relation_type": "RUBIN_1_6T_NIC_COMPOSED_OF_DUAL_800G_CX9"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
processor	Rubin	04_knowledge_base/Vera Rubin
network_interface	NIC	NIC
nic_package	CX-9	ConnectX-9
host_cpu	Vera CPU	04_knowledge_base/NVIDIA Vera CPU
host_link	PCIe Gen 6.0	PCIe

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。