VR2R-0562_r1

VR2R-0562

① SA Source

• Source: 開啟完整 SA 文章
• Section: Scale-Up Network - NVLink 6
• Line hint: 470

Context Before

High speed signals require better PCB materials, especially for NVLink 6 which has much lower tolerance for insertion loss given the use of bidirectional signaling.

Evidence

The number of lanes between the PaladinHD2 connectors and the NVLink Switch also creates complexity for PCB design.

Context After

Hence, the NVLink 6 Switch board PCB is upgraded to 32 layers with M8+ graded CCL—minimally LDK2 glass fiber cloth or potentially Quartz fiber cloth.

② Atomic Claim

PaladinHD2 connectors 與 NVLink Switch 之間的 lane 數量，也提高了 PCB design complexity。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/Paladin connector",
        "label": "PaladinHD2"
      },
      "role": "connector"
    },
    {
      "node": {
        "id": "04_knowledge_base/NVLink",
        "label": "NVLink"
      },
      "role": "switch_interconnect"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCB",
        "label": "PCB"
      },
      "role": "board"
    }
  ],
  "qualifiers": {
    "condition_text": "lane count between PaladinHD2 connectors and NVLink Switch",
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "relation_type": "LANE_COUNT_DRIVES_PCB_DESIGN_COMPLEXITY"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
connector	PaladinHD2	04_knowledge_base/Paladin connector
switch_interconnect	NVLink	NVLink
board	PCB	PCB

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。