VR2R-0561_r1

VR2R-0561

① SA Source

• Source: 開啟完整 SA 文章
• Section: Scale-Up Network - NVLink 6
• Line hint: 470

Context Before

Each of the green lines in the reference topology represents nine 400G logical ports of NVLink 6, or 18 TX/RX lanes of 200G. Because there is only 1 DP per lane using bidirectional SerDes, there are a total of 18 DPs between any connector and any switch for a total of 72 DPs per connector, which is the same as prior generation of NVLink 5 Switch Tray.

Evidence

High speed signals require better PCB materials, especially for NVLink 6 which has much lower tolerance for insertion loss given the use of bidirectional signaling.

Context After

The number of lanes between the PaladinHD2 connectors and the NVLink Switch also creates complexity for PCB design. Hence, the NVLink 6 Switch board PCB is upgraded to 32 layers with M8+ graded CCL—minimally LDK2 glass fiber cloth or potentially Quartz fiber cloth.

② Atomic Claim

High-speed signals 需要更好的 PCB materials；尤其 NVLink 6 因採 bidirectional signaling，對 insertion loss 的 tolerance 更低。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/NVLink",
        "label": "NVLink 6"
      },
      "role": "interconnect"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCB",
        "label": "PCB"
      },
      "role": "board_material"
    }
  ],
  "qualifiers": {
    "condition_text": "lower insertion-loss tolerance under bidirectional signaling",
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "relation_type": "NVLINK6_BIDIRECTIONAL_SIGNALING_REQUIRES_BETTER_PCB_MATERIALS"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
interconnect	NVLink 6	NVLink
board_material	PCB	PCB

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。