VR2R-0560
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Scale-Up Network - NVLink 6 - Line hint:
468
Context Before
Each of the green lines in the reference topology represents nine 400G logical ports of NVLink 6, or 18 TX/RX lanes of 200G. Because there is only 1 DP per lane using bidirectional SerDes, there are a total of 18 DPs between any connector and
Evidence
any switch for a total of 72 DPs per connector, which is the same as prior generation of NVLink 5 Switch Tray.
Context After
High speed signals require better PCB materials, especially for NVLink 6 which has much lower tolerance for insertion loss given the use of bidirectional signaling. The number of lanes between the PaladinHD2 connectors and the NVLink Switch also creates complexity for PCB design. Hence, the NVLink 6 Switch board PCB is upgraded to 32 layers with M8+ graded CCL—minimally LDK2 glass fiber cloth or potentially Quartz fiber cloth.
② Atomic Claim
……任一 switch 之間，因此每個 connector 合計 72 個 DPs；這與前一代 NVLink 5 Switch Tray 相同。
- Epistemic Mode:
ASSERTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"attribute": "REFERENCE_DP_COUNT_PER_CONNECTOR",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/NVLink5",
"label": "NVLink 5"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": "continuation of VR2R-0559; current topology entity is implicit",
"numeric_mentions": [
"72"
],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"72"
],
"value_text": "the current topology totals 72 DPs per connector, the same as the prior NVLink 5 Switch Tray."
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | NVLink 5 | NVLink5 |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。