VR2R-0542_r1

VR2R-0542

① SA Source

• Source: 開啟完整 SA 文章
• Section: Scale-Up Network - NVLink 6
• Line hint: 454

Context Before

The bidirectional SerDes technology employed on the copper backplane is used for NVIDIA’s scale-up network.

Evidence

For Vera Rubin NVL72, the scale-up network continues to be rail-optimized with all-to-all connectivity between each GPU and switch ASIC in the scale-up domain.

Context After

NVIDIA’s GB200 scale-up architecture consists of 18 NVLink 5 Switch chips in a single rack for the NVL72 system.

② Atomic Claim

對 Vera Rubin NVL72，scale-up network 繼續採 rail-optimized design，scale-up domain 中每顆 GPU 與 switch ASIC 之間都是 all-to-all connectivity。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/Vera Rubin",
        "label": "Vera Rubin"
      },
      "role": "platform"
    },
    {
      "node": {
        "id": "04_knowledge_base/GPU",
        "label": "GPU"
      },
      "role": "compute"
    },
    {
      "node": {
        "id": "04_knowledge_base/ASIC",
        "label": "ASIC"
      },
      "role": "switch_silicon"
    }
  ],
  "qualifiers": {
    "condition_text": "rail-optimized scale-up domain",
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "relation_type": "VERA_RUBIN_SCALE_UP_ALL_TO_ALL_GPU_SWITCH_CONNECTIVITY"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
platform	Vera Rubin	04_knowledge_base/Vera Rubin
compute	GPU	GPU
switch_silicon	ASIC	ASIC

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。