VR2R-0520
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Bi-directional SerDes for Scale-Up - Line hint:
428
Context Before
The doubling of bandwidth per logical GPU from NVLink 5 in GB300 NVL72 to NVLink 6 in Vera Rubin NVL72 are made possible by using a simultaneous bi-directional SerDes for the copper backplane instead of increasing the modulation or baud rate. Whereas NVLink 5 delivers 224G per electrical lane, NVLink 6.0 delivers 448G per electrical lane.
Evidence
Each electrical lane is one differential pair (DP) consisting of two conductors that carry equal magnitude, and opposite polarity signals.
Context After
This gives rise to the engineering problem of ensuring that a clean signal can be received at either end of the wire because two signals sent in opposite directions over the same copper wire will superpose to form a composite signal that is different from the intended transmitting signal.
② Atomic Claim
每個 electrical lane 是一組 differential pair（DP），由兩條 conductors 組成，兩者承載 magnitude 相等、polarity 相反的 signals。
- Epistemic Mode:
ASSERTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"frame_type": "CLAIM_ONLY",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"2"
],
"temporal_mentions": []
},
"reason": "GENERAL_DIFFERENTIAL_PAIR_DEFINITION_WITHOUT_CANONICAL_ENTITY",
"statement": "each electrical lane is one differential pair consisting of two conductors carrying equal-magnitude, opposite-polarity signals."
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| — | — | — |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。