VR2R-0519_r1

VR2R-0519

① SA Source

• Source: 開啟完整 SA 文章
• Section: Bi-directional SerDes for Scale-Up
• Line hint: 428

Context Before

The doubling of bandwidth per logical GPU from NVLink 5 in GB300 NVL72 to NVLink 6 in Vera Rubin NVL72 are made possible by using a simultaneous bi-directional SerDes for the copper backplane instead of increasing the modulation or baud rate.

Evidence

Whereas NVLink 5 delivers 224G per electrical lane, NVLink 6.0 delivers 448G per electrical lane.

Context After

Each electrical lane is one differential pair (DP) consisting of two conductors that carry equal magnitude, and opposite polarity signals.

② Atomic Claim

NVLink 5 每個 electrical lane 為 224G；NVLink 6.0 則為 448G。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "comparison_expression": "NVLink 5 delivers 224G per electrical lane versus 448G for NVLink 6.0.",
  "entities": [
    {
      "id": "04_knowledge_base/NVLink5",
      "label": "NVLink 5"
    },
    {
      "id": "04_knowledge_base/NVLink",
      "label": "NVLink 6.0"
    }
  ],
  "frame_type": "COMPARISON",
  "metric": "BANDWIDTH_PER_ELECTRICAL_LANE",
  "operator": "GREATER_THAN",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "224G",
      "448G"
    ],
    "temporal_mentions": []
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	NVLink 5	NVLink5
entity	NVLink 6.0	NVLink

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。