VR2R-0518_r1

VR2R-0518

① SA Source

• Source: 開啟完整 SA 文章
• Section: Bi-directional SerDes for Scale-Up
• Line hint: 428

Context Before

Evidence

The doubling of bandwidth per logical GPU from NVLink 5 in GB300 NVL72 to NVLink 6 in Vera Rubin NVL72 are made possible by using a simultaneous bi-directional SerDes for the copper backplane instead of increasing the modulation or baud rate.

Context After

Whereas NVLink 5 delivers 224G per electrical lane, NVLink 6.0 delivers 448G per electrical lane. Each electrical lane is one differential pair (DP) consisting of two conductors that carry equal magnitude, and opposite polarity signals.

② Atomic Claim

從 GB300 NVL72 的 NVLink 5 到 Vera Rubin NVL72 的 NVLink 6，每個 logical GPU 的 bandwidth 翻倍；原文認為這是藉由 copper backplane 上 simultaneous bi-directional SerDes 達成，而不是提高 modulation 或 baud rate。

• Epistemic Mode: HYPOTHETICAL
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/GPU",
        "label": "GPU"
      },
      "role": "gpu"
    },
    {
      "node": {
        "id": "04_knowledge_base/NVLink5",
        "label": "NVLink 5"
      },
      "role": "previous_interconnect"
    },
    {
      "node": {
        "id": "04_knowledge_base/GB300",
        "label": "GB300"
      },
      "role": "previous_platform"
    },
    {
      "node": {
        "id": "04_knowledge_base/NVLink",
        "label": "NVLink 6"
      },
      "role": "new_interconnect"
    },
    {
      "node": {
        "id": "04_knowledge_base/Vera Rubin",
        "label": "Vera Rubin"
      },
      "role": "new_platform"
    },
    {
      "node": {
        "id": "04_knowledge_base/SerDes",
        "label": "SerDes"
      },
      "role": "signaling"
    },
    {
      "node": {
        "id": "04_knowledge_base/Backplane",
        "label": "backplane"
      },
      "role": "medium"
    }
  ],
  "qualifiers": {
    "condition_text": "source presents this mechanism hypothetically; instead of increasing modulation or baud rate",
    "numeric_mentions": [
      "2x"
    ],
    "temporal_mentions": []
  },
  "relation_type": "BIDIRECTIONAL_SERDES_ENABLES_NVLINK_BANDWIDTH_DOUBLING"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
gpu	GPU	GPU
previous_interconnect	NVLink 5	NVLink5
previous_platform	GB300	GB300
new_interconnect	NVLink 6	NVLink
new_platform	Vera Rubin	04_knowledge_base/Vera Rubin
signaling	SerDes	SerDes
medium	backplane	Backplane

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。