VR2R-0404
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Compute Tray: Power Delivery - Line hint:
336
Context Before
50VDC enters the Strata Board via one of the 50V power connectors on both sides of the Strata board. 50VDC is stepped down to 12VDC by the IBC module at the bottom of the Strata Board.
Evidence
Context After
Strata directly receives 50VDC whereas the Bianca board of Grace Blackwell receives 12VDC from the PDB.
② Atomic Claim
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/VRM",
"label": "VRM"
},
"role": "voltage_regulator"
},
{
"node": {
"id": "04_knowledge_base/Vera Rubin",
"label": "Rubin"
},
"role": "accelerator"
},
{
"node": {
"id": "04_knowledge_base/GPU",
"label": "GPU"
},
"role": "accelerator_type"
},
{
"node": {
"id": "04_knowledge_base/NVIDIA Vera CPU",
"label": "Vera CPU"
},
"role": "cpu"
}
],
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"12VDC",
"1VDC"
],
"temporal_mentions": []
},
"relation_type": "VRM_STEPS_12V_TO_1V_FOR_PROCESSORS"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| voltage_regulator | VRM | VRM |
| accelerator | Rubin | 04_knowledge_base/Vera Rubin |
| accelerator_type | GPU | GPU |
| cpu | Vera CPU | 04_knowledge_base/NVIDIA Vera CPU |
⑤ Human Review
請在 Properties 逐項確認:
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。