VR2R-0402_r1

VR2R-0402

① SA Source

• Source: 開啟完整 SA 文章
• Section: Compute Tray: Power Delivery
• Line hint: 336

Context Before

The internal busbar cables will feed 50VDC power to a busbar device that travels under the PCB midplane to connect to the power distribution board (PDB) on the other side of the PCB midplane. This differs from Grace Blackwell, where 50VDC power goes directly to the PDB. Then, the PDB feeds 12VDC to all the boards in the compute tray.

Evidence

50VDC enters the Strata Board via one of the 50V power connectors on both sides of the Strata board.

Context After

50VDC is stepped down to 12VDC by the IBC module at the bottom of the Strata Board. Then the 12VDC will be stepped down to 1VDC by the VRM before feeding into the Rubin GPU and Vera CPU. Strata directly receives 50VDC whereas the Bianca board of Grace Blackwell receives 12VDC from the PDB.

② Atomic Claim

50VDC 會透過 Strata Board 兩側的 50V power connectors 進入 Strata Board。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "POWER_INPUT",
  "context_nodes": [],
  "entity": {
    "id": "04_knowledge_base/NVIDIA Strata Board",
    "label": "Strata Board"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": "connectors on both sides",
    "numeric_mentions": [
      "50VDC",
      "50V"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "50VDC",
      "50V"
    ],
    "value_text": "50VDC enters through 50V power connectors on both sides of the Strata board."
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	Strata Board	04_knowledge_base/NVIDIA Strata Board

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。