VR2R-0299_r1

VR2R-0299

① SA Source

• Source: 開啟完整 SA 文章
• Section: PCB vs Flyover Cables
• Line hint: 270

Context Before

First, we must understand why high-speed signals perform worse on PCB versus flyover cables.

Evidence

As SerDes rates increase, high-speed channels become increasingly constrained by insertion loss introduced by PCB traces, vias, dielectric materials and conductor roughness.

Context After

Insertion loss is defined as the signal power that is lost as a signal is traveling through an interconnect channel.

② Atomic Claim

隨著 SerDes rates 提高，high-speed channels 越來越受到 PCB traces、vias、dielectric materials 與 conductor roughness 所帶來 insertion loss 的限制。

• Epistemic Mode: ASSERTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/SerDes",
        "label": "SerDes"
      },
      "role": "high_speed_interface"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCB",
        "label": "PCB"
      },
      "role": "routing_medium"
    }
  ],
  "qualifiers": {
    "condition_text": "traces, vias, dielectric materials and conductor roughness are plain text in source claim",
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "relation_type": "HIGHER_SERDES_RATE_INCREASES_PCB_INSERTION_LOSS_CONSTRAINT"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
high_speed_interface	SerDes	SerDes
routing_medium	PCB	PCB

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。