VR2R-0297_r1

VR2R-0297

① SA Source

• Source: 開啟完整 SA 文章
• Section: PCB vs Flyover Cables
• Line hint: 268

Context Before

Nevertheless, it is still challenging to drive a PCIe Gen6 signal over around 500mm of PCB distance from the Strata Module to the front of the Orchid Module.

Evidence

In addition to having high quality SerDes, proper signal integrity is still achievable by upgrading PCB materials.

Context After

First, we must understand why high-speed signals perform worse on PCB versus flyover cables. As SerDes rates increase, high-speed channels become increasingly constrained by insertion loss introduced by PCB traces, vias, dielectric materials and conductor roughness. Insertion loss is defined as the signal power that is lost as a signal is traveling through an interconnect channel.

② Atomic Claim

除了需要高品質 SerDes，透過升級 PCB materials，仍可達成適當的 signal integrity。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/SerDes",
        "label": "SerDes"
      },
      "role": "serdes"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCB",
        "label": "PCB"
      },
      "role": "routing_medium"
    }
  ],
  "qualifiers": {
    "condition_text": "requires high-quality SerDes and upgraded PCB materials",
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "relation_type": "SERDES_AND_PCB_MATERIAL_ENABLE_SIGNAL_INTEGRITY"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
serdes	SerDes	SerDes
routing_medium	PCB	PCB

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。