VR2R-0132_r1

VR2R-0132

① SA Source

• Source: 開啟完整 SA 文章
• Section: NVLink 6 Switch
• Line hint: 105

Context Before

While the rack-level switching bandwidth has doubled, the number of NVLink Switch chips per rack has also doubled to 36, with each switch tray now housing 4 Switch chips. This means the new NVLink 6 Switch chip has the same 28.8T bandwidth as NVLink5 Switch, with half the number of ports but running at double the rate using ‘400G’ bi-directional SerDes. This allows the high bandwidth switch design to remain as a single monolithic die, saving on design complexity.

Evidence

The layout remains the same as NVIDIA’s previous switches, with 2 sides for IO and a central logic section crossbar and 3.6 TFlop SHARP in-network compute acceleration.

Context After

② Atomic Claim

Layout 維持與 NVIDIA 前代 switches 相同：兩側為 I/O，中間是 logic-section crossbar，並提供 3.6 TFlop SHARP in-network compute acceleration。

• Epistemic Mode: ASSERTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "attribute": "SWITCH_LAYOUT_AND_SHARP_COMPUTE",
  "context_nodes": [],
  "entity": {
    "id": "02_companies/NVDA",
    "label": "NVIDIA"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": "switch/layout/SHARP 未 canonicalized",
    "numeric_mentions": [
      "2",
      "3.6 TFlop"
    ],
    "temporal_mentions": [
      "previous switches"
    ]
  },
  "value": {
    "numeric_mentions": [
      "2",
      "3.6 TFlop"
    ],
    "value_text": "two I/O sides, central logic crossbar, and 3.6 TFlop SHARP in-network compute acceleration."
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	NVIDIA	NVDA

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。