VR2R-0125_r1

VR2R-0125

① SA Source

• Source: 開啟完整 SA 文章
• Section: Vera
• Line hint: 99

Context Before

L3 cache also received a 40% capacity bump to 162MB. Memory bus width doubled to 1024-bit and speed increased to 9600MT/s for 2.5x bandwidth, while maximum capacity tripled to 1.5TB with 8 SOCAMM modules.

Evidence

The NVLink-C2C to the Rubin GPUs also doubled in bandwidth to 1.8TB/s.

Context After

PCIe6 and CXL3.1 are now supported as well. All this results in transistor count increasing 2.2x to 227 billion.

② Atomic Claim

連到 Rubin GPUs 的 NVLink-C2C bandwidth 也加倍至 1.8TB/s。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/NVLink-C2C",
        "label": "NVLink-C2C"
      },
      "role": "interconnect"
    },
    {
      "node": {
        "id": "04_knowledge_base/Vera Rubin",
        "label": "Rubin"
      },
      "role": "platform"
    },
    {
      "node": {
        "id": "04_knowledge_base/GPU",
        "label": "GPU"
      },
      "role": "device"
    }
  ],
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "2x",
      "1.8TB/s"
    ],
    "temporal_mentions": []
  },
  "relation_type": "NVLINK_C2C_BANDWIDTH_TO_RUBIN_GPU"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
interconnect	NVLink-C2C	NVLink-C2C
platform	Rubin	04_knowledge_base/Vera Rubin
device	GPU	GPU

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。