VR2R-0123_r1

VR2R-0123

① SA Source

• Source: 開啟完整 SA 文章
• Section: Vera
• Line hint: 99

Context Before

NVIDIA was aggressive on the CPU front, with Vera doubling performance over Grace by moving to a 3nm reticle-sized compute die and disaggregating the memory controllers and I/O into chiplets. Core count increases from 72 to 88, with 91 cores printed on die to leave redundancy for yield improvement. These cores mark the return of NVIDIA’s custom ARM CPU designs, with the ‘Olympus’ core now supporting SMT multi-threading for a total of 176 processing threads.

Evidence

L3 cache also received a 40% capacity bump to 162MB.

Context After

Memory bus width doubled to 1024-bit and speed increased to 9600MT/s for 2.5x bandwidth, while maximum capacity tripled to 1.5TB with 8 SOCAMM modules. The NVLink-C2C to the Rubin GPUs also doubled in bandwidth to 1.8TB/s. PCIe6 and CXL3.1 are now supported as well. All this results in transistor count increasing 2.2x to 227 billion.

② Atomic Claim

L3 cache capacity 也增加 40%，達到 162MB。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "CAPACITY_CHANGE",
  "context_nodes": [],
  "entity": {
    "id": "04_knowledge_base/L3 cache",
    "label": "L3 cache"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "40%",
      "162MB"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "40%",
      "162MB"
    ],
    "value_text": "capacity 增加 40% 至 162MB。"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	L3 cache	04_knowledge_base/L3 cache

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。