VR2R-0122
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Vera - Line hint:
97
Context Before
NVIDIA was aggressive on the CPU front, with Vera doubling performance over Grace by moving to a 3nm reticle-sized compute die and disaggregating the memory controllers and I/O into chiplets. Core count increases from 72 to 88, with 91 cores printed on die to leave redundancy for yield improvement.
Evidence
Context After
L3 cache also received a 40% capacity bump to 162MB. Memory bus width doubled to 1024-bit and speed increased to 9600MT/s for 2.5x bandwidth, while maximum capacity tripled to 1.5TB with 8 SOCAMM modules. The NVLink-C2C to the Rubin GPUs also doubled in bandwidth to 1.8TB/s. PCIe6 and CXL3.1 are now supported as well. All this results in transistor count increasing 2.2x to 227 billion.
② Atomic Claim
這些 cores 代表 NVIDIA custom ARM CPU design 回歸;「Olympus」core 現在支援 SMT multi-threading,總計 176 processing threads。
- Epistemic Mode:
ASSERTED - Mapping Status:
PARTIAL
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "02_companies/NVDA",
"label": "NVIDIA"
},
"role": "vendor"
},
{
"node": {
"id": "04_knowledge_base/CPU",
"label": "CPU"
},
"role": "processor_category"
},
{
"node": {
"id": "04_knowledge_base/SMT",
"label": "SMT"
},
"role": "multithreading"
}
],
"qualifiers": {
"condition_text": "Olympus core 未 canonicalized",
"numeric_mentions": [
"176"
],
"temporal_mentions": [
"now"
]
},
"relation_type": "CUSTOM_ARM_CPU_SMT_SUPPORT"
}④ Canonical Entity Mapping
⑤ Human Review
請在 Properties 逐項確認:
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。