VR2R-0080_r1

VR2R-0080

① SA Source

• Source: 開啟完整 SA 文章
• Section: Rubin
• Line hint: 69

Context Before

The NVLink-C2C chiplet houses the SerDes for the Vera CPU connection, doubled in bandwidth to 1.8TB/s, while the larger NVLink 6 chiplet on the other end of the chip features 36 custom ‘400G’ SerDes links for 2x NVLink bandwidth to all 72 Rubin GPUs.

Evidence

Transistor count has climbed 60% to 336 billion.

Context After

A notable omission from Rubin is the mention of Sparse FLOPs. In previous generations, 2:4 structured sparsity was used to double marketing FLOPs numbers. However, adoption was minimal especially at low precisions due to accuracy losses from the rigid sparsity structure forcing half of the values to be zero. Programmers basically ignored structured sparsity as it was not useful, which caused hardware designs to change as well.

② Atomic Claim

Transistor count 增加 60%，達到 336 billion。

• Epistemic Mode: ASSERTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "frame_type": "CLAIM_ONLY",
  "qualifiers": {
    "condition_text": "本 atomic claim 未明示裝置主詞",
    "numeric_mentions": [
      "60%",
      "336 billion"
    ],
    "temporal_mentions": []
  },
  "reason": "DEVICE_SUBJECT_IMPLICIT_IN_EXTRACTION",
  "statement": "Transistor count 增加 60%，達到 336 billion。"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
—	—	—

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。